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| MCH6202-TL资料 | |
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MCH6202-TL PDF Download |
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File Size : 116 KB
Manufacturer:PANASONIC Description: The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. An Output Enable (OE) input is provided for three-state control of the outputs. The frequencies of both the RCLK and the WCLK signals may vary from 0 to fMAX with complete independence. There are no restrictions on the frequency of the one clock input with respect to the other. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：MCH6202-TL 厂 家：PANASONIC 封 装：SOT-363 批 号： 数 量：2770 说 明：绝对全新原装大量现货，质量保证，欢迎来电查询 |
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运 费： 所在地： 新旧程度： |
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| 联系人：李利媛 |
| 电 话：0755/83019596,83247541,83247486 |
| 手 机：13480648723 |
| QQ：1104562168,1178139673,1113496577,2881934444,2881943289,2881943290 |
| MSN：ao-liteng01@hotmail.com,ao-liteng02@hotmail.com,ao-liteng03@hotmail.com,ao-liteng04@hotmail.com |
| 传 真：0755-83016216 |
| EMail：aoliteng1@163.com |
| 公司地址： 广东省深圳市福田区振兴西路新欣大厦B座518室 |
