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MBRA210LT3G

MBRA210LT3G资料
MBRA210LT3G
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Description:The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and has software flow control and hardware flow control capabilities.
 
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型 号:MBRA210LT3G
厂 家:
封 装:
批 号:09+
数 量:30000
说 明:全新原装正品现货,专业供应
 
 
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