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| IRLR3715Z资料 | |
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IRLR3715Z PDF Download |
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File Size : 116 KB
Manufacturer:IR Description:TXENABLE has two purposes. In all modes, TXENABLE must be high for the DATA to the DAC to be enabled. When TXENABLE is low, the digital logic section is forced to all 0, and any input data presented to DA[15:0] and DB[15:0] is ignored. In interleaved data mode, when the qflag register bit is cleared, TXENABLE is used to synchronizes the data to channels A and B. The first data after the rising edge of TXENABLE is treated as A data, while the next data is treated as B data, and so on. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：IRLR3715Z 厂 家：IR 封 装：2009+ 批 号：200000 数 量：D-PAK 说 明：全新原装现货特价供应 欢迎来电查询 |
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