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HY57V561620CT-7资料 | |
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HY57V561620CT-7 PDF Download |
File Size : 116 KB
Manufacturer:HYNIX Description: Device is continuously selected. OE, CE1 = VIL. CE2 = VIH. WE is HIGH for read cycle. Data I/O is High Z if OE = VIH, CE1 = VIH, WE = VIL, or CE2=VIL. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. CE1 and WE must be LOW and CE2 must be HIGH to initiate write. A write can be terminated by CE1 or WE going HIGH or CE2 going LOW. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 14. During this period, the I/Os are in the output state and input signals should not be applied. |
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1PCS | 100PCS | 1K | 10K | ||
价 格 | |||||
型 号:HY57V561620CT-7 厂 家:HYNIX 封 装: 批 号:09+ 数 量:30000 说 明:全新原装正品现货,专业供应 |
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运 费: 所在地: 新旧程度: |
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联系人:李利媛 |
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公司地址: 广东省深圳市福田区振兴西路新欣大厦B座518室 |