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| EPM7128ALC84-6资料 | |
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EPM7128ALC84-6 PDF Download |
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File Size : 116 KB
Manufacturer:ALTERA Description:Notes: (1) Reset until clock pulse 18 (on declining flank). Minimum integration time = (133-18) * CLK period + 10µs (this is the time the S&H cap needs to follow). At 1MHz clock speed, the minimum integration time becomes 0.125ms. (2) At 125C, the integration time should be limited to 2ms. (3) The SI pulse must go low before the rising edge of the next clock pulse. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：EPM7128ALC84-6 厂 家：ALTERA 封 装：PLCC 批 号：09+ 数 量：5000 说 明：绝对全新原装正品现货，欢迎新老客户来电！！ |
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