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| EPM7128AETC144-5资料 | |
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EPM7128AETC144-5 PDF Download |
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File Size : 116 KB
Manufacturer:ALTERA Description:non-repetitive data patterns. However, the transmission of SYNC patterns enables the Deserializer to lock to the Seri- alizer signal within a specified time. See Figure 16. The users application determines control of the SYNC1 and SYNC 2 pins. One recommendation is a direct feedback loop from the LOCK pin. Under all circumstances, the Serializer stops sending SYNC patterns after both SYNC inputs return low. When the Deserializer detects edge transitions at the Bus LVDS input, it will attempt to lock to the embedded clock information. When the Deserializer locks to the Bus LVDS clock, the LOCK output will go low. When LOCK is low, the Deserializer outputs represent incoming Bus LVDS data. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：EPM7128AETC144-5 厂 家：ALTERA 封 装：QFP 批 号：09+ 数 量：5000 说 明：绝对全新原装正品现货，欢迎新老客户来电！！ |
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