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EPM7064AETI100-10

EPM7064AETI100-10资料
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File Size : 116 KB Manufacturer:ALTERA Description: The ?C?A/S/L and ?C?A/S?H inputs internally generate a ?C?A/S signal functioning in a similar manner to the single ?C?A/S input of other DRAMs. The key difference is each ?C?A/S input ( ?C?A/S/L and ?C?A/S?H ) controls its corresponding 8 DQ inputs during WRITE accesses. ?C?A/S/L controls DQ1 through DQ8 and ?C?A/S?H controls DQ9 through DQ16. The two ?C?A/S controls give the MT4LC1M16E5(S) both BYTE READ and BYTE WRITE cycle capabilities. A logic HIGH on ?W/E dictates READ mode while a logic LOW on ?W/E dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE or ?C?A/S (?C?AS/L or ?C?A/S/H), whichever occurs last. An EARLY WRITE/ occurs when WE is taken LOW prior to either ?C?A/S falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE falls after ?C?A/S (?C?A/S/L or ?C?A/S/H) was taken LOW. During EARLY WRITE cycles, the data-outputs (Q) will remain High-Z regardless of the state of ?O/E. During LATE WRITE or READ-MODIFY-WRITE cycles, ?O/E must be taken HIGH to disable the data-outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping ?O/E LOW, no write will occur, and the data-outputs will drive read data from the accessed location. The 16 data inputs and 16 data outputs are routed through 16 pins using common I/O. Pin direction is controlled by ?O/E and ?W/E.

	1PCS	100PCS	1K	10K
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型号：EPM7064AETI100-10 厂家：ALTERA 封装：QFP 批号：09+ 数量：6000 说明：★全新原装正品现货，价格优势★


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