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| EPM7064AELC44-10资料 | |
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EPM7064AELC44-10 PDF Download |
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File Size : 116 KB
Manufacturer:ALTERA Description:ASYNCHRONOUS OPERATION For asynchronous operation, separate transmit and receive clocks may be applied. MCLKX and MCLKR must be 2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the TP3054, and need not be synchronous. For best transmis- sion performance, however, MCLKR should be synchronous with MCLKX, which is easily achieved by applying only static logic levels to the MCLKR/PDN pin. This will automatically connect MCLKX to all internal MCLKR functions (see Pin Description). For 1.544 MHz operation, the device automati- cally compensates for the 193rd clock pulse each frame. FSX starts each encoding cycle and must be synchronous with MCLKX and BCLKX. FSR starts each decoding cycle and must be synchronous with BCLKR. BCLKR must be a clock, the logic levels shown in Table 1 are not valid in asynchronous mode. BCLKX and BCLKR may operate from 64 kHz to 2.048 MHz. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：EPM7064AELC44-10 厂 家：ALTERA 封 装：PLCC 批 号：09+ 数 量：6000 说 明：★全新原装正品现货，价格优势★ |
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