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| EP1K10TC100-2N资料 | |
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EP1K10TC100-2N PDF Download |
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File Size : 116 KB
Manufacturer:ALTERA Description:Notes: 1. Worst case values occur at an IC junction temperature of 125C. 2. For designers who do not need to read from the display, the Read line can be tied to VDD and the Write and Chip Enable lines can be tied together. 3. Changing the logic levels of the Address lines when CE = "0" may cause erroneous data to be entered into the Character RAM, regardless of the logic levels of the WR and RD lines. 4. The display must not be accessed until after 3 clock pulses (110 µs min. using the internal refresh clock) after the rising edge of the reset line. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：EP1K10TC100-2N 厂 家：ALTERA 封 装：QFP 批 号：09+ 数 量：5000 说 明：全新原装现货特价供应欢迎来电查询 |
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