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| DM74LS161AN资料 | |
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DM74LS161AN PDF Download |
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File Size : 116 KB
Manufacturer:MC Description:Two independent LVDS receiver serial ports for optional 1:1 protection Main and redundant LVDS transmit ports Loop timing capability enables LVDS recovered clock to internally drive LVDS transmit clock Internal buffers allow maximum LVDS serial bit rate independent of UTOPIA clock rate Programmable UTOPIA interface UTOPIA Level 2 up to 52 MHz ATM layer or PHY layer interface ATM layer interface can support up to 248 standard Level 2 PHY ports with no additional external circuitry. Configured as 31 MPHYs, each with up to 8 sub-ports Supports extended cell size up to 64 bytes Supports 16- or 8-bit data buses with parity Embedded bidirectional, non-blocking flow control over serial link for per MPHY back pressure No external memories required Embedded OAM channel over serial link Remote Alarm/Status Indications Link Trace Label Embedded Control Channel with flow control for software communication BIP16 based error performance monitoring In protected systems, the standby link OAM channel is available for embedded communications and performance/alarm monitoring Multiple loop-back options Standard microprocessor interface (Intel and Motorola compatible) IEEE 1149.1 JTAG port Temperature range: −40˚C to +85˚C CMOS technology for low power LVDS transceiver section uses 3.3V power supply. Digital UTOPIA section uses 2.5V power supply. All I/O are 3.3V tolerant. 196 LBGA package, 15x15x1.37 mm, 1.0 mm ball pitch |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：DM74LS161AN 厂 家：MC 封 装：DIP 批 号：09+ 数 量：30000 说 明：全新原装正品现货，专业供应 |
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运 费： 所在地： 新旧程度： |
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| 联系人：李利媛 |
| 电 话：0755/83019596,83247541,83247486 |
| 手 机：13480648723 |
| QQ：1104562168,1178139673,1113496577,2881934444,2881943289,2881943290 |
| MSN：ao-liteng01@hotmail.com,ao-liteng02@hotmail.com,ao-liteng03@hotmail.com,ao-liteng04@hotmail.com |
| 传 真：0755-83016216 |
| EMail：aoliteng1@163.com |
| 公司地址： 广东省深圳市福田区振兴西路新欣大厦B座518室 |
技术支持:维库电子市场网