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| ACL2520L-R39J-T资料 | |
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ACL2520L-R39J-T PDF Download |
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File Size : 116 KB
Manufacturer:TDK Description:• 1.8V+0.1V/-0.1V Power Supply. • DLL circuitry for wide output data valid window and future freguency scaling. • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ -0.1V for 1.8V I/O. • Separate independent read and write data ports • HSTL I/O • Synchronous pipeline read with self timed late write. • Registered address, control and data input/output. • Full data coherency, providing most current data. • DDR(Double Data Rate) Interface on read and write ports. • Fixed 2-bit burst for both read and write operation. • Clock-stop supports to reduce current. • Two input clocks(K and K) for accurate DDR timing at clock rising edges only. • Two input clocks for output data(C and C) to minimize clock-skew and flight-time mismatches. • Two echo clocks (CQ and CQ) to enhance output data traceability. • Single address bus. • Byte write (x18, x36) function. • Simple depth expansion with no data contention. • Programmable output impedance. • JTAG 1149.1 compatible test access port. • 165FBGA(11x15 ball array FBGA) with body size of 13x15mm |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：ACL2520L-R39J-T 厂 家：TDK 封 装：2520-390N 批 号： 数 量：5 说 明：绝对全新原装大量现货，质量保证，欢迎来电查询 |
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运 费： 所在地： 新旧程度： |
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| 联系人：李利媛 |
| 电 话：0755/83019596,83247541,83247486 |
| 手 机：13480648723 |
| QQ：1104562168,1178139673,1113496577,2881934444,2881943289,2881943290 |
| MSN：ao-liteng01@hotmail.com,ao-liteng02@hotmail.com,ao-liteng03@hotmail.com,ao-liteng04@hotmail.com |
| 传 真：0755-83016216 |
| EMail：aoliteng1@163.com |
| 公司地址： 广东省深圳市福田区振兴西路新欣大厦B座518室 |
技术支持:维库电子市场网